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286 IP
201
0.118
UMC 40nm LP Dual Port SRAM compiler with Sleep/Retention mode
UMC 40nm LP Dual Port SRAM compiler with Sleep/Retention mode...
202
0.118
UMC 40nm LP Logic Process Dual-Port SRAM Memory Compiler with LVT peripheral
UMC 40nm LP Logic Process Dual-Port SRAM Memory Compiler with LVT peripheral...
203
0.118
UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy
UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy...
204
0.118
UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy and LVT peripheral
UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy and LVT peripheral...
205
0.118
UMC 40nm LP Logic Process Single Port SRAM memory compiler using 213 bit -cell with peri-HVT
UMC 40nm LP Logic Process Single Port SRAM memory compiler using 213 bit -cell with peri-HVT...
206
0.118
UMC 40nm LP Logic Process Single Port SRAM Memory Compiler using 213 bit-cell with Peri-LVT
UMC 40nm LP Logic Process Single Port SRAM Memory Compiler using 213 bit-cell with Peri-LVT...
207
0.118
UMC 40nm LP Logic Process standard synchronous high density dual port SRAM memory compiler with LVT
UMC 40nm LP Logic Process standard synchronous high density dual port SRAM memory compiler with LVT...
208
0.118
UMC 40nm LP Logic Process standard synchronous high density dual port SRAM memory compiler with ROW redundancy with LVt peripheral
UMC 40nm LP Logic Process standard synchronous high density dual port SRAM memory compiler with ROW redundancy with LVt peripheral...
209
0.118
UMC 40nm LP Logic Process TCAM with LVT peripheral memory compiler
UMC 40nm LP Logic Process TCAM with LVT peripheral memory compiler...
210
0.118
UMC 40nm LP Logic Process ULL Single Port SRAM Memory Compiler using 213 bit-cell with peri-HVT
UMC 40nm LP Logic Process ULL Single Port SRAM Memory Compiler using 213 bit-cell with peri-HVT...
211
0.118
UMC 40nm LP Logic Process ULL Single Port SRAM Memory Compiler using 213 bit-cell with peri-LVT
UMC 40nm LP Logic Process ULL Single Port SRAM Memory Compiler using 213 bit-cell with peri-LVT...
212
0.118
UMC 40nm LP LowK Logic Process ULL Dual-Port SRAM Memory Compiler with Peri-LVT
UMC 40nm LP LowK Logic Process ULL Dual-Port SRAM Memory Compiler with Peri-LVT...
213
0.118
UMC 40nm LP process standard synchronous high density TCAM memory compiler.
UMC 40nm LP process standard synchronous high density TCAM memory compiler....
214
0.118
UMC 40nm LP process synchronous high density (0.213LPHVT cell) single port SRAM compiler with row redundancy.
UMC 40nm LP process synchronous high density (0.213LPHVT cell) single port SRAM compiler with row redundancy....
215
0.118
UMC 40nm LP with power gating & peri-HVT 1PRF
UMC 40nm LP with power gating & peri-HVT 1PRF...
216
0.118
UMC 40nm uLP process ULL One Port Register File memory compiler
UMC 40nm uLP process ULL One Port Register File memory compiler...
217
0.118
UMC 40nm uLP process ULL Single-Port SRAM
UMC 40nm uLP process ULL Single-Port SRAM...
218
0.118
UMC 55nm eFlash eFlash Dual-Port SRAM Memory Compiler
UMC 55nm eFlash eFlash Dual-Port SRAM Memory Compiler...
219
0.118
UMC 55nm EFLASH Process Dual-Port SRAM Memory Compiler
UMC 55nm EFLASH Process Dual-Port SRAM Memory Compiler...
220
0.118
UMC 55nm eFlash Process Dual-Port SRAM with Row redundancy
UMC 55nm eFlash Process Dual-Port SRAM with Row redundancy...
221
0.118
UMC 55nm eFlash process process synchronous low power feature RVT peripheral high density single port SRAM compiler.
UMC 55nm eFlash process process synchronous low power feature RVT peripheral high density single port SRAM compiler....
222
0.118
UMC 55nm eFlash process synchronous low power feature RVT peripheral high density single port SRAM compiler with row redundancy.
UMC 55nm eFlash process synchronous low power feature RVT peripheral high density single port SRAM compiler with row redundancy....
223
0.118
UMC 55nm EFLASH Processy Single-Port SRAM with row repair Memory complier
UMC 55nm EFLASH Processy Single-Port SRAM with row repair Memory complier...
224
0.118
UMC 55nm eFlash Single-Port SRAM memory compiler
UMC 55nm eFlash Single-Port SRAM memory compiler...
225
0.118
UMC 55nm eflash/ulp process standard synchronous high density single port SRAM memory compiler.
UMC 55nm eflash/ulp process standard synchronous high density single port SRAM memory compiler....
226
0.118
UMC 55nm eHV process ; Single-Port SRAM compiler with Row redundancy
UMC 55nm eHV process ; Single-Port SRAM compiler with Row redundancy...
227
0.118
UMC 55nm eHV Process Single Port SRAM Memory Compiler with Peripheral H/LVT using 277 bit-cell
UMC 55nm eHV Process Single Port SRAM Memory Compiler with Peripheral H/LVT using 277 bit-cell...
228
0.118
UMC 55nm eHV Process Single Port SRAM with row redundancy for 277cell
UMC 55nm eHV Process Single Port SRAM with row redundancy for 277cell...
229
0.118
UMC 55nm eHV process;Single-Port SRAM compiler
UMC 55nm eHV process;Single-Port SRAM compiler...
230
0.118
UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high density single port SRAM memory compiler with row redundancy.
UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high density single port SR...
231
0.118
UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high density single port SRAM memory compiler.
UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high density single port SR...
232
0.118
UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT+uHVT periphery high density single port SRAM memory compiler with row redundancy.
UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT+uHVT periphery high density single po...
233
0.118
UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT+uHVT periphery high density single port SRAM memory compiler.
UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT+uHVT periphery high density single po...
234
0.118
UMC 55nm Low-K/Low-Power Logic process synchronous ultra-high-speed single-port SRAM compiler.
UMC 55nm Low-K/Low-Power Logic process synchronous ultra-high-speed single-port SRAM compiler....
235
0.118
UMC 55nm LP process with PG Dual port SRAM compiler
UMC 55nm LP process with PG Dual port SRAM compiler...
236
0.118
UMC 55nm SST process standard synchronous high density single port SRAM memory compiler.
UMC 55nm SST process standard synchronous high density single port SRAM memory compiler....
237
0.118
UMC 55nm SST/ulp Logic process standard synchronous high density single port SRAM memory compiler.
UMC 55nm SST/ulp Logic process standard synchronous high density single port SRAM memory compiler....
238
0.118
UMC 55nm ULP Low-K process, Single-Port SRAM with Row repair & periphery HVT
UMC 55nm ULP Low-K process, Single-Port SRAM with Row repair & periphery HVT...
239
0.118
UMC 55nm ULP process , Single-Port SRAM with row repair and HVT
UMC 55nm ULP process , Single-Port SRAM with row repair and HVT...
240
0.118
UMC 55nm ULP-SST process standard synchronous high density single port SRAM memory compiler.
UMC 55nm ULP-SST process standard synchronous high density single port SRAM memory compiler....
241
0.118
UMC 55nm ULP-SST process standard synchronous high density single port SRAM memory compiler.
UMC 55nm ULP-SST process standard synchronous high density single port SRAM memory compiler....
242
0.118
UMC 55nm ULP/LowK process Single-Port SRAM
UMC 55nm ULP/LowK process Single-Port SRAM...
243
0.118
UMC 55nm ULP/LowK process Single-Port SRAM
UMC 55nm ULP/LowK process Single-Port SRAM...
244
0.118
UMC 55nm ULP/LowK Process Single-Port SRAM with RED Well Biase Memory compiler
UMC 55nm ULP/LowK Process Single-Port SRAM with RED Well Biase Memory compiler...
245
0.118
UMC 55nm ULP/LowK Process Single-Port SRAM with well bias & RED Memory Compiler
UMC 55nm ULP/LowK Process Single-Port SRAM with well bias & RED Memory Compiler...
246
0.118
UMC 55nm ULP/LowK Process Single-Port SRAM with well bias HVT Memory Compiler
UMC 55nm ULP/LowK Process Single-Port SRAM with well bias HVT Memory Compiler...
247
0.118
UMC 55nm ULP/LowK Single-Port SRAM with Well Bias uHVT
UMC 55nm ULP/LowK Single-Port SRAM with Well Bias uHVT...
248
0.118
UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler with redundancy.
UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler with redundancy....
249
0.118
UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler.
UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler....
250
0.118
UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler.
UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler....
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